1. Field of the Invention
The present invention relates to a read-out circuit for use with semiconductor memory devices and, more particularly, to a read-out circuit comprising first selecting means for selectively reading data from a plurality of memory means; first data storing means for storing the data read out by the selecting means; transferring means for transferring the data stored in the first data storing means in synchronism with an external clock signal; second data storing means for storing the data sent from the transferring means; and second selecting means for selectively outputting to an output port the data stored in the second data storing means.
2. Description of the Prior Art
Image memories generally contain both a group of matrix type memory cells (e.g., DRAM or SRAM memory array) that are randomly accessible, and serial registers that are serially accessible. The two sets of memory elements are interfaced through the so-called read-out circuit. The typical prior art read-out circuit is illustratively constructed as shown in FIG. 7.
In FIG. 7, reference characters SA represent a sense amplifier each. Each sense amplifier amplifies the data that is read from a memory cell to a bit line BL. The data coming from the memory cell and amplified by the sense amplifier SA is transferred through first selecting means (comprising column selectors Qc, Qc, . . . ) to first data storing means F.F.D. The data storing means F.F.D is illustratively a single-bit register made of a flip-flop device.
The data stored in the first data storing means F.F.D is transferred to second data storing means F.F.S in synchronism with an external clock signal. More specifically, the data is transferred via an MOS transistor Qt that is switched in accordance with a transfer signal T.
The second data storing means F.F.S is illustratively a single-bit register comprised of a flip-flop device. The data stored in the second data storing means F.F.S is read out onto a data bus via second selecting means (containing Y selectors Qy, Qy, . . . ) receiving a Y select signal Y.
In this setup, a single-bit register is provided for a plurality (n) of bit pairs constituting a single block BLK. There are m blocks for which are furnished m single-bit registers that make up an m-bit serial register. Illustratively, the number m is 4.
In the read-out circuit of FIG. 7 for use with a semiconductor memory device (image memory), the capacity on the output side of the column selectors Qc, Qc, . . . (output side of the first data storing means F.F.D) typically becomes too large to be driven adequately by the small sense amplifier SA. The reason for this is as follows: An n-bit (e.g., 128- or 256-bit) column decoder connected to a single line inevitably increases the parasitic capacity of that line. The line with such a boosted parasitic capacity, when driven by one tiny sense amplifier SA, prolongs the time it takes to switch the column selector output line level from 0 to 1 or 1 to 0. The direction of the level transition depends on whether the MOS transistor constituting each column selector gate is of n-channel type or p-channel type.
With more time required for line level changeover, the time it takes to read data is also prolonged. More specifically, since each column selector gate usually contains an n-channel MOS transistor Qc, the performance margin involved is worsened when a 1 (a high level) is to be transferred. That is, the transition from 1 to 0 is quick but the reverse takes time. If the column selector were composed of a CMOS arrangement, this problem would not be experienced. However, such a measure makes the layout of the device so difficult to achieve that efforts to attain high integration are seriously hampered.